A Review on Performance Analysis of CMOS Inverter

Authors

  • Saurabh Kumar Singh Student, Madan Mohan Malaviya University of Technology, Gorkhpur, Uttar Pradesh,
  • Mangal Deep Student, Madan Mohan Malaviya University of Technology, Gorkhpur, Uttar Pradesh,
  • R.K. Chauhan Student, Madan Mohan Malaviya University of Technology, Gorkhpur, Uttar Pradesh,

DOI:

https://doi.org/10.37628/jcam.v5i1.907

Keywords:

Inverter circuits, power, delay, area, noise margin, VLSI

Abstract

In this paper, first we study the various inverter circuits and analyze its performance in terms of noise margin, area, power dissipation and computational delay. After that analyze the various parameter of CMOS Inverter circuit using Pyxis schematic tools of Mentor graphics with TSMC 018 CMOS process technology. Based on this simulation, analyze the rise time, fall time and dynamic power dissipation of CMOS inverter. Finally, we got the good relationship between them such as rise time or fall time is directly proportional to the load capacitor and inversely proportional to gate capacitance of PMOS and NMOS transistor, and also find the parameter which causes dynamic power dissipation.

References

Saurabh Kumar Singh, Mangal Deep, R.K. Chauhan. A review on performance analysis of CMOS inverter. International Journal of Computer Aided Manufacturing. 2019; 5(1): 29–35p.

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Published

2019-07-18

Issue

Vol. 5 No. 1 (2019)

Section

Articles